Dispatch 010 — Architecture Licensing

ARM and the Architecture Licensing Layer

Published June 9, 2026
Primary Class — Shovel / Gatekeeper Hybrid
Layer — Architecture Licensing Infrastructure
Confidence — High

ARM does not manufacture chips. It licenses the processor architecture that chip designers build against — the instruction set, the IP blocks, the compatibility framework — so that software written once runs across billions of devices from different manufacturers. That position is not a product. It is a structural layer beneath every mobile device, embedded system, cloud server, and AI accelerator that depends on ARM-compatible processor design.

Executive Intelligence Brief
ARM Holdings plc is classified under the Shovel Economy Framework as a Hybrid: Shovel (primary) / Gatekeeper (moderate). ARM operates the architecture licensing layer: it licenses processor instruction set architectures (ISA) and processor IP to semiconductor companies, device makers, cloud hyperscalers, and chip designers worldwide. Its structural position is Shovel-primary because it enables many unrelated downstream participants — mobile SoC designers, automotive chip makers, embedded developers, AI accelerator builders, and cloud hyperscalers — simultaneously, regardless of which specific devices or applications win their respective markets. It carries Gatekeeper characteristics because the ARM ISA creates a software compatibility layer that concentrates ecosystem gravity: applications, operating systems, compilers, and toolchains built on ARM's architecture create significant switching costs for any actor seeking to migrate to an alternative instruction set.
Critical distinction from TSMC and ASML: ARM's Gatekeeper signal is classified as moderate, not strong. The existence of RISC-V — an open-source, royalty-free instruction set architecture governed by RISC-V International — limits ARM's absolute access-control ceiling. For new platforms where software compatibility constraints are lower, RISC-V is a credible structural alternative. This is the primary source of classification uncertainty in this dossier.
Primary Layer
Shovel
Enables chip designers across unrelated markets; earns royalties on aggregate volume regardless of which devices win.
Gatekeeper Signal
Moderate
ISA ecosystem creates real switching costs; RISC-V limits the absolute control ceiling vs. TSMC-class structural monopoly.
Speculation Exposure
Very Low
ARM earns royalties per chip shipped across all its licensees; it does not depend on any single market wave or device category winning.
Replacement Difficulty
High
ISA migration requires software ecosystem rebuild, toolchain replacement, and binary compatibility breaks — year-to-decade scale. RISC-V reduces this to "High" rather than "Very High."
Scanner Output
The scanner classification for ARM emphasizes four dominant signals: near-core infrastructure position (processor architecture underlies all computing devices), broad enablement across unrelated markets, high necessity relative to speculation, and strong dependency compounding through ecosystem integrations. The Gatekeeper secondary signal reflects ISA compatibility concentration, moderated by the structural existence of RISC-V as an alternative path.
Miner16 / 100
Shovel88 / 100
Gatekeeper73 / 100
Classification Summary

Structural Classification Record

This is the scanner-derived classification record for ARM Holdings plc as of the date of this dossier. Classifications should be re-evaluated when ARM's market share in server architecture changes materially, when RISC-V ecosystem maturity reaches parity with ARM's in a major device segment, or when a structural shift in mobile SoC design alternatives occurs.
Actor
ARM Holdings plc
Actor Type
Company — Processor Architecture and IP Licensor
Market Wave
Semiconductor / Mobile / AI / Edge / Automotive
Primary Classification
Hybrid — Shovel (primary) / Gatekeeper (moderate)
Confidence Level
High Confidence
Scanner Scores
Miner: 16 · Shovel: 88 · Gatekeeper: 73
Classification Date
2026-06-09
Classification Version
Scanner Engine 2H-20260609
Signal Source
Manual analysis — ARM-specific signal calibration
Preset Available
No — ARM preset not yet added to scanner engine
To reproduce or test this classification, open the Shovel Scanner and configure signals manually using the values documented in Section 12 (Scanner Interpretation).
Framework Position

Why ARM Belongs in the Shovel Economy

The Shovel Economy thesis holds that durable value during any market wave is often captured not by the actors competing in the visible race, but by the infrastructure layer that enables participation in that race. ARM's position is a precise instance of this pattern — but it operates at a layer that is more abstract, and therefore easier to misread, than physical infrastructure like TSMC's fabs or ASML's lithography machines.

The Architecture Layer Is Infrastructure

A processor architecture is not a product. It is a specification — a defined language that describes how a processor interprets instructions and how software communicates with hardware. When ARM licenses its instruction set architecture (ISA) to chip designers, those designers can build processors that are compatible with any software compiled for ARM-based systems. The architecture is the invisible infrastructure beneath the chip, beneath the device, and beneath the application.

Without an architecture layer, no chip design can begin. A chip that cannot execute software intelligibly is not a processor — it is a pattern on silicon. The architecture layer converts hardware into computation. ARM holds the licensing position over that layer for the majority of mobile devices, the growing majority of embedded systems and automotive controllers, and an expanding portion of cloud server infrastructure. That makes ARM a shovel-layer asset: it supplies the enabling layer to chip designers across all downstream markets without competing for any of those markets itself.

ARM Earns From the Rush, Not From a Winner

ARM's revenue structure is defined by two streams: upfront licensing fees paid when a company licenses ARM's architecture or processor IP, and royalties paid per chip shipped. Source: ARM Holdings Form 20-F (SEC filing, 2023) — T1. The royalty stream is the structural signal: ARM earns from every ARM-architecture chip produced, regardless of whether that chip is in a phone that outsells its competitors, a wearable that fails commercially, or a server that displaces incumbent x86 infrastructure.

This is the definitional shovel-layer economic structure. The gold rush — whether it is mobile computing, edge AI, automotive electrification, or cloud infrastructure expansion — does not determine ARM's royalty income by picking a winner. It determines ARM's royalty income by expanding the total volume of ARM-architecture chips produced. That is not speculation exposure. That is infrastructure capture. See the Shovel Economy Framework for the structural framework that classifies this pattern.

ARM does not build
the processors.
It licenses the architecture
all processors speak.
That position — creating the shared specification language that chip designers depend on to maintain software compatibility — is a structural layer distinct from manufacturing, equipment, and application development. It is the architecture licensing layer: a position that compounds as more devices are built on ARM-compatible designs.
Historical Position

From Architecture Design
to Licensing Layer

ARM's structural position did not emerge suddenly. It was built through three decades of sustained licensing expansion across successive computing waves. Understanding the history is necessary to understand why the current position is durable rather than contingent on any single product cycle.

1990 — The Dedicated Architecture Licensing Model Is Founded [High Confidence — T1]

ARM Holdings was founded in November 1990 as Advanced RISC Machines Ltd., a joint venture between Acorn Computers, Apple Computer, and VLSI Technology. Source: ARM corporate history (ARM official investor relations, T1). The founding thesis was structural: instead of building complete processors for sale, ARM would license the processor architecture and IP to other companies, allowing them to integrate ARM-designed or ARM-compatible processors into their own chips and devices. ARM itself would not manufacture silicon.

This was a direct analogy to the foundry model that TSMC was demonstrating in the same period: separate the design or specification layer from the manufacturing layer. ARM's version was even further upstream — it separated the architecture specification layer from both chip design and manufacturing. Every participant in the chain (chip designer, foundry, device maker) could specialize, while ARM earned from the aggregate volume of all of them.

1998 — Public Listing; Architecture Becomes Market Infrastructure [High Confidence — T1]

ARM Holdings plc listed simultaneously on the London Stock Exchange and NASDAQ in April 1998. Source: Company and exchange records (T1). By this point, the ARM architecture had been adopted by a substantial number of embedded and mobile semiconductor companies. The mobile computing wave — initially personal digital assistants, then increasingly mobile phones — was creating a demand for low-power processor architectures that ARM's RISC design principles were well-suited to serve.

The 1998 IPO made ARM's licensing model visible as a public business. But the more structurally significant development of this period was the gradual convergence of the mobile semiconductor ecosystem around a small number of ARM-compatible designs. Qualcomm, Samsung, and subsequently MediaTek were building mobile SoCs on ARM architecture — consistent with ARM Holdings Form 20-F customer disclosures (T1); analyst interpretation for the broader ecosystem consolidation narrative. The ecosystem was consolidating around ARM's ISA — not because any single actor mandated it, but because software compatibility across devices created a gravitational pull that favored architectural standardization.

2007–2016 — Mobile Wave Cements the Architecture Layer [High Confidence — T1/T3]

The smartphone era transformed ARM from a broadly-adopted embedded architecture into the infrastructure layer of global mobile computing. Apple's introduction of the iPhone in 2007 placed an ARM-architecture processor at the center of a globally transformative mobile product category. Apple licensed ARM's architecture and designed its own custom processor microarchitecture — the approach that would eventually produce the A-series chips in iPhone and the M-series chips in Mac. Source: Apple official product announcements (T1) for Apple Silicon transition; ARM corporate history for architecture license (T1).

SoftBank Group acquired ARM Holdings in 2016 for approximately £23.4 billion. Source: regulatory approval records and public company disclosures (T1). The acquisition reflected SoftBank's thesis that ARM's architecture licensing layer would compound in value as the number of connected devices expanded beyond mobile into IoT, automotive, and industrial computing. The acquisition did not change ARM's licensing model — it changed ARM's ownership while the structural position remained intact.

2020–2022 — NVIDIA Acquisition Attempt Collapses; Neutrality Protected [High Confidence — T1]

NVIDIA announced the acquisition of ARM from SoftBank in September 2020 for approximately $40 billion. The deal was abandoned in February 2022 following opposition from the UK Competition and Markets Authority (CMA), the European Commission, and the US Federal Trade Commission (FTC). Source: Regulatory body announcements and company disclosures (T1).

The regulatory blocking of this transaction is itself a structural signal. Multiple competition regulators determined that NVIDIA's ownership of ARM would create structural conflicts of interest for ARM's role as a neutral architecture licensor. ARM licenses its architecture to companies that compete directly with each other — including companies that compete with NVIDIA. Regulators assessed that this neutrality was the foundation of ARM's structural position: customers would accept architectural dependency on ARM because ARM was not a competitor. NVIDIA ownership would eliminate that assurance. Analyst interpretation: the regulatory outcome preserved a structural feature — ARM's neutrality — that is itself a precondition for the depth of ARM's licensing position.

2023 — Re-IPO and Cloud Architecture Expansion [High Confidence — T1]

ARM Holdings re-listed on NASDAQ in September 2023. Source: ARM Holdings Form 20-F (SEC filing, 2023) — T1. The re-IPO coincided with a structural expansion of ARM's market position into cloud server infrastructure, where ARM-architecture processors had previously had limited penetration against Intel and AMD's x86 architecture dominance. Amazon Web Services (AWS) Graviton, Google Axion, and Microsoft Azure Cobalt — all ARM architecture-based custom server processors — represented a structural migration of cloud computing infrastructure toward ARM architecture. Each of these represents a T1-backed product announcement from the respective company; AWS Graviton first announced in 2018 with successive generations, Google Axion announced in 2024, Microsoft Cobalt 100 announced in 2023. These represent public confirmations of architectural migration at scale in cloud infrastructure — a market that was previously dominated by x86.

Current Structural Position

Five Dimensions of Structural Authority

Infrastructure Capture

ARM operates the architecture licensing layer for processor design. Its products divide into two principal license types: (1) Architecture Licenses, which allow licensees to design custom processor microarchitectures compatible with the ARM ISA (used by Apple, Amazon, Qualcomm, Google, NVIDIA, and others for custom CPU designs), and (2) IP/Processor Licenses, which provide pre-designed CPU cores — Cortex-A for mobile/server, Cortex-M for microcontrollers, Cortex-R for real-time embedded, Neoverse for cloud and infrastructure — for integration into SoC designs. Source: ARM Holdings Form 20-F (2023), T1.

The architecture layer sits beneath chip manufacturing, beneath chip design, and beneath all software: it is the lowest-level commercial infrastructure in computing after the physics of transistors. ARM's position at this layer is what produces the classification as a shovel-layer asset: it is closer to core infrastructure than any application, platform, or even most physical manufacturing participants.

Control Mechanisms — The Software Compatibility Layer

ARM's primary control mechanism is not contractual. It is ecological. The ARM ISA has accumulated decades of software compatibility — applications, operating system kernels, compilers, toolchains, debuggers, and developer workflows built to target ARM architecture. This compatibility layer means that a device shipping an ARM-architecture processor can run any software compiled for ARM without modification. A device that migrates to a different ISA must rebuild or recompile this entire software stack.

In mobile computing, the Android and iOS ecosystems are built predominantly on ARM architecture. In embedded systems, substantial quantities of firmware and safety-critical code are compiled for ARM Cortex-M and Cortex-R targets. In cloud computing, the migration of AWS Graviton, Google Axion, and Microsoft Cobalt represents deliberate investment in ARM-architecture compatibility for cloud workloads — investment that deepens the ecosystem lock-in over time. Analyst interpretation: these cumulative software ecosystem investments are the dominant switching cost, not ARM's licensing contracts themselves.

Switching Cost Architecture and Dependency Compounding

Switching from ARM architecture to an alternative ISA (RISC-V, x86, or a proprietary ISA) requires: (1) full software stack recompilation or rewriting for workloads that cannot be automatically compiled cross-architecture, (2) toolchain and developer environment migration, (3) binary compatibility breaks affecting third-party software and libraries, (4) re-certification for safety-critical applications in automotive and industrial contexts, and (5) ecosystem rebuild for partner IP, design tools, and reference designs aligned to ARM's AMBA bus protocol and other architectural standards. Analyst interpretation.

Dependency compounding follows from ARM's multi-market position: as AI inference moves to edge devices, automotive electrification adds compute requirements to vehicles, IoT expansion adds more microcontroller-class ARM implementations, and cloud server adoption of ARM Neoverse grows — all of these trends increase the aggregate volume of ARM-compatible chips shipped and deepen the software ecosystem built around the ARM ISA. This is the compounding dynamic described in the durability analysis: infrastructure that grows more valuable as adoption expands across more independent market segments.

Architecture Licensing Layer

What Makes This Layer Distinct

The architecture licensing layer is structurally distinct from manufacturing infrastructure, equipment infrastructure, and application-layer platforms. Understanding the distinction is necessary to classify ARM accurately within the Shovel Economy and to avoid misreading its structural position.

Architecture License
The Custom CPU Path
An architecture license grants the licensee the right to design a custom processor microarchitecture that implements the ARM ISA — the internal pipeline, cache hierarchy, branch predictor, power management — while producing a processor that is software-compatible with any ARM ISA compliant system. Apple's M-series and A-series chips, Amazon's Graviton series, Qualcomm's Oryon processor, and Google's Axion are all built on ARM architecture licenses. The licensee owns the microarchitecture; ARM owns the ISA specification they build against. Royalties are paid per chip shipped.
IP / Processor License
The Pre-Designed Core Path
A processor IP license provides a pre-designed CPU core — Cortex-M0 through Cortex-M85 for microcontrollers, Cortex-A series for mobile and server applications, Cortex-R for real-time embedded — that the licensee integrates into their SoC alongside memory controllers, interconnects, accelerators, and peripheral logic. The licensee designs the system around the ARM core; ARM designs the core itself. This path serves the majority of ARM's license count: hundreds of semiconductor companies building products for IoT, industrial, automotive, and consumer electronics markets. Royalties are paid per chip shipped.
What ARM Controls
The ISA Specification
ARM controls the specification of the instruction set: the binary encoding of instructions, the defined behavior of the processor state machine, the calling conventions, the memory model, and the privileged architecture that operating systems depend on. This specification is the compatibility layer. Software compiled to target AArch64 (ARM's 64-bit ISA) runs on any processor — Apple silicon, AWS Graviton, Qualcomm Snapdragon — that correctly implements AArch64. The specification is ARM's structural asset; the compilers, OS kernels, and applications that target it are the ecosystem that creates the switching cost.
What ARM Does Not Control
Manufacturing and Microarchitecture
ARM does not manufacture chips, does not operate fabs, does not own equipment, and does not compete for chip design wins in any end market. The physical manufacturing of every ARM-architecture chip depends on TSMC, Samsung Foundry, or other fabs. The specific performance of a given ARM-architecture processor depends on the microarchitecture decisions of the licensee. ARM's structural position is defined by what it does control — the ISA layer — and is not weakened by what it does not control. This separation is the same logic that makes the foundry model structurally powerful: specialization at a layer creates compounding depth within that layer.
Dependency Map

What Depends on ARM.
What ARM Depends On.

ARM sits at the architecture layer: dependent on a set of upstream technical and commercial infrastructure providers, while being the primary architecture dependency for chip designers across mobile, embedded, server, automotive, and AI hardware markets. This two-directional dependency structure defines ARM's structural node position in the global computing supply chain.

Upstream — What ARM Depends On

Analyst interpretation based on semiconductor industry structure. ARM's upstream dependencies are less physical than TSMC's or ASML's — they are primarily commercial, technical, and ecosystem-based.

  • EDA Tool Vendors (Synopsys, Cadence, Siemens EDA) — Electronic design automation tools are required for chip designers to synthesize, simulate, and verify ARM IP against target foundry processes. ARM's IP must be compatible with the major EDA flows. Analyst interpretation.
  • Semiconductor Foundries (TSMC, Samsung Foundry, others) — ARM's IP must be characterized and validated against foundry process design kits (PDKs) to be usable by licensees. When a licensee uses an ARM Cortex core, they need ARM's IP qualified for the specific foundry node they are using. See Dispatch 009 (TSMC) for the manufacturing layer classification.
  • Standards Bodies (AMBA, ISA governance) — ARM's AMBA (Advanced Microcontroller Bus Architecture) bus protocol is an industry standard for SoC interconnect design. ARM contributes to and depends on ecosystem-level standards adoption for its IP to remain the default design substrate.
  • Compiler Toolchains (GCC, LLVM/Clang, MSVC) — ARM architecture value depends on compiler support. The GCC and LLVM projects provide open-source compilers that target ARM architecture; without compiler support, the ISA's software compatibility value would not exist. ARM contributes engineering to these projects. Analyst interpretation.
  • Operating System Kernels (Linux, Android, iOS, RTOS vendors) — ARM architecture requires OS kernel ports that implement the privileged architecture specification. The Linux kernel, Android, iOS, and major RTOS (real-time operating system) vendors maintain ARM architecture support. This is not a dependency ARM controls, but it is a precondition for the ecosystem value of ARM's ISA.
Downstream — What Depends on ARM
  • Apple — A-series processors (iPhone, iPad) and M-series processors (Mac, iPad Pro) are designed on ARM architecture licenses. Apple's entire device silicon portfolio is ARM ISA-compatible. Source: Apple official product announcements (T1).
  • Qualcomm — Snapdragon mobile SoCs and Oryon custom CPU cores for Windows on ARM PCs are designed on ARM architecture. Source: Qualcomm official product announcements and ARM licensing documentation (T1). Customer relationship consistent with ARM Form 20-F disclosures.
  • MediaTek — Mobile SoCs for a large portion of global smartphone production use ARM Cortex IP. ARM's Form 20-F (2023) identifies MediaTek as a significant customer. Source: ARM Holdings Form 20-F (2023), T1.
  • Amazon Web Services (AWS) — Graviton processor series (Graviton, Graviton2, Graviton3, Graviton4) are ARM Neoverse architecture-based. Source: AWS official press releases (T1).
  • Google — Axion processor for Google Cloud infrastructure is ARM-based (announced 2024). Source: Google Cloud official announcements (T1).
  • Microsoft — Azure Cobalt 100 processor for Azure infrastructure is ARM Neoverse-based. Source: Microsoft Azure official announcements (T1).
  • NVIDIA — NVIDIA Grace CPU (Hopper architecture server platform) uses ARM Neoverse V2 architecture. Source: NVIDIA official product announcements (T1).
  • Automotive chip suppliers (NXP, Renesas, STMicroelectronics) — ARM Cortex-R and Cortex-A cores are used in automotive microcontrollers and SoCs for ADAS, powertrain, and body electronics. Analyst interpretation; consistent with ARM's automotive market materials.
  • Embedded and IoT suppliers (Nordic Semiconductor, Microchip, Silicon Labs) — ARM Cortex-M microcontrollers are the dominant processor architecture for IoT, wearable, and embedded applications. Analyst interpretation; consistent with ARM Form 20-F market segment disclosures.
  • Samsung Semiconductor — Exynos mobile processors are designed on ARM architecture. Customer relationship consistent with ARM Form 20-F disclosures (T1).
Replacement Difficulty

Why Replacing ARM
Takes Years, Not Months

Replacement Difficulty: High
ARM's replacement difficulty is assessed as High — one level below TSMC's Very High — because RISC-V constitutes a credible structural alternative path, especially for new platforms where software compatibility is less constraining. The distinction matters: TSMC's replacement difficulty is Very High because there is no alternative provider of leading-edge fabrication. ARM's replacement difficulty is High because there is an alternative ISA; the migration cost is real and substantial, but not physically impossible the way replacing TSMC's unique process capability would be.
Alternatives
RISC-V is a credible and growing alternative ISA governed by RISC-V International (T2 — standards body). It is open-source, royalty-free, and has documented adoption in embedded controllers and initial data center applications. Companies including Western Digital and SiFive have publicly adopted RISC-V for specific applications (T3 — technology press reporting; analyst interpretation). In some regions, government-motivated policy objectives are accelerating RISC-V adoption as an alternative to licensed architecture IP — analyst interpretation; specific penetration figures are not sourced in this dossier with High Confidence. x86 (Intel/AMD) remains dominant in desktop and traditional server markets but is not a credible substitute for ARM's mobile, embedded, and automotive footprint. No single alternative matches ARM's combination of ecosystem maturity, software compatibility, and multi-market breadth at time of writing. Analyst interpretation.
Migration Cost Type
Software ecosystem migration (recompilation or rewriting of applications, OS kernels, firmware), toolchain migration (compiler targets, debuggers, profilers), binary compatibility breaks (existing compiled software will not run on a different ISA without recompilation or emulation), safety recertification for automotive and industrial applications (ARM Cortex-R and Cortex-A have accumulated functional safety certifications), and design ecosystem migration (AMBA bus protocols, reference IP, partner ecosystem). Analyst interpretation: all cost types must be absorbed simultaneously for a full platform migration.
Migration Timeline
Years to decade-scale for established platforms with large accumulated software ecosystems. New platforms (a purpose-built AI accelerator with no prior software compatibility requirement, for example) could adopt RISC-V or a custom ISA without the full migration cost. This asymmetry — high migration cost for established platforms, lower for greenfield — is the structural reason ARM's replacement difficulty is classified as High rather than Very High. Analyst interpretation.
Historical Evidence
Apple's transition from Intel x86 to Apple Silicon (ARM architecture) in 2020–2021 demonstrates that ISA migration for a major platform is achievable — but required multiple years of preparation, Rosetta 2 binary translation software, developer toolchain updates, and a coordinated multi-release migration strategy. Source: Apple official announcements (T1). The evidence cuts both ways: it proves ISA migration is possible (supporting RISC-V as a long-run alternative), and it demonstrates that even a well-resourced and technically capable company requires multiple years of preparation for a platform-scale ISA transition.
Fragility Factors
ARM's two structural fragility factors are: (1) RISC-V trajectory — if RISC-V achieves ecosystem maturity parity with ARM in a major segment (most likely: AI accelerators, then embedded, then cloud), the gatekeeper signal will diminish. This is the primary long-term structural risk to ARM's classification. (2) Geopolitical fragility — ARM is headquartered in the UK with operations in the US and globally; significant restriction on ARM's licensing to specific regions (as has occurred in related semiconductor policy contexts) could accelerate alternative ISA adoption in those regions. Watch Signal — neither fragility factor is assessed as near-term by available evidence.
Control-Layer and Shovel-Layer Analysis

Structural Authority Decomposed

Shovel-Layer Signals
Enabling Many Participants
ARM enables Apple, Qualcomm, MediaTek, Samsung, Amazon, Google, Microsoft, NVIDIA, NXP, Renesas, and hundreds of smaller chip designers simultaneously. These companies compete directly with each other in mobile, cloud, and embedded markets. ARM's structural position improves as all of them grow — it captures aggregate chip volume, not outcome-specific revenue. The definition of a shovel-layer asset: benefit from the race without needing a specific winner. ARM's royalty income is determined by total ARM-architecture chip production volume across all its licensees — a structurally diversified position that would survive the commercial failure of any individual licensee.
Gatekeeper-Layer Signals
ISA Ecosystem as Access Control
The ARM ISA is the software compatibility layer around which decades of applications, operating systems, compilers, and developer workflows have been built. Any device or platform that seeks to be software-compatible with existing ARM-based systems must either implement ARM's ISA (paying royalties) or maintain binary translation/emulation layers (adding cost and performance overhead). This creates a de facto access control: to participate in the ARM ecosystem without ARM's license, the cost is either paying ARM or accepting incompatibility. The gatekeeper signal is real, but its strength is moderated by RISC-V as an exit path for new platforms. See the Control Layer analysis.
Compounding Dynamics
Ecosystem Deepens With Adoption
Each new device category that adopts ARM architecture adds software ecosystem depth. Mobile computing built the Android and iOS software layers on ARM. Edge AI adoption extends neural network inference frameworks to ARM-architecture targets. Automotive safety certification creates decades-long commitments to ARM-certified IP. Cloud infrastructure migration (Graviton, Axion, Cobalt) extends datacenter workloads to ARM-compiled software. Each of these transitions deepens the ecosystem value of ARM's ISA — the more software is built against ARM architecture, the higher the migration cost for any actor considering an alternative. This is the compounding dynamic described in the Shovel Economy Framework.
Where Gatekeeper Strength Is Limited
RISC-V and Greenfield Platforms
ARM's gatekeeper position weakens at the boundaries of its existing ecosystem: (1) Greenfield AI accelerators designed without software compatibility requirements can choose RISC-V for non-application-processor control cores without incurring ecosystem migration costs. (2) In some regions, policy-motivated interest in domestic semiconductor alternatives has been associated with accelerated RISC-V adoption in specific markets — Analyst interpretation. (3) Any new computing category that does not need to be software-compatible with existing ARM systems faces a lower barrier to RISC-V adoption. The key structural question for future classification reviews: if RISC-V achieves dominant adoption in one major segment, does the precedent reduce ARM's gatekeeper signal in adjacent segments? Analyst interpretation — Watch Signal.
Future Projects and Forward Watch Layer

Publicly Announced Forward Initiatives

The following projects meet the Intelligence Standard's four-gate requirement: publicly announced by the actor or a government body, source-backed with a citable reference, date-checked, and clearly distinguished from analyst inference. Items not meeting all four gates are labeled Watch Signal.

ARM Neoverse Platform — Cloud and Infrastructure Expansion [High Confidence — T1]

ARM publicly announced and has continued to develop the Neoverse platform — a family of processor IP products targeting cloud, infrastructure, and edge computing. The Neoverse N series targets balanced workloads; the Neoverse V series targets high-performance computing and AI inference workloads. Successive generations (N1, N2, V1, V2) have been announced and are in production. Source: ARM official product announcements and investor relations materials (T1). AWS Graviton, Google Axion, Microsoft Azure Cobalt 100, and NVIDIA Grace are all documented implementations of ARM Neoverse-based designs — confirmed by official announcements from each company (T1).

Structural implication: the Neoverse platform represents ARM's entry into server and cloud infrastructure — a market previously dominated by x86 (Intel Xeon, AMD EPYC). Confirmed adoption by three of the largest cloud infrastructure operators (AWS, Google, Microsoft) is a T1-supported signal of structural migration in cloud compute architecture. The depth and trajectory of this migration is a Watch Signal — current adoption is confirmed but future market share trajectory in server infrastructure is not deterministic.

ARM Compute Subsystems (CSS) — System-Level IP [High Confidence — T1]

ARM announced its Compute Subsystems (CSS) program as a system-level IP offering providing validated, pre-integrated subsystem designs — combining ARM CPU cores with AMBA interconnects, memory interfaces, and system infrastructure — to accelerate SoC design. CSS extends ARM's IP licensing model beyond individual CPU cores to integrated system-level building blocks. Source: ARM official product documentation and press releases (T1).

Structural implication: CSS represents an expansion of ARM's IP capture depth — instead of licensing a CPU core, ARM licenses a validated multi-component system. This increases the value of each license and deepens the per-chip integration of ARM IP into SoC designs, which compounds both the royalty revenue per chip and the switching cost for licensees.

ARM Total Design Ecosystem — Custom Silicon Acceleration [High Confidence — T1]

ARM announced the Arm Total Design ecosystem in October 2022, a program designed to accelerate the development of custom silicon using ARM IP, partner IP, EDA tools, and foundry process libraries. The program includes participation from major cloud companies, EDA vendors, and foundry partners. Source: ARM official press release (October 2022), T1.

Structural implication: Total Design extends ARM's position from an IP licensor to an ecosystem orchestrator for custom chip development — reducing the time-to-tape-out for companies building custom silicon on ARM architecture. This lowers the technical barrier for companies to adopt ARM architecture for custom chips, which expands ARM's potential licensee base, but also potentially accelerates RISC-V competition for the same custom silicon segment. Analyst interpretation.

Automotive Safety Certification Expansion — Watch Signal [Watch Signal — T3]

ARM has publicized ongoing work to achieve functional safety certifications (ISO 26262 for automotive) for its Cortex-R and Cortex-A series products targeting automotive ADAS and powertrain applications. Source: ARM official product documentation (T1) for the existence of these efforts. Specific new certification completions and customer adoption timelines in automotive are not fully confirmed in primary sources at the date of this dossier — Watch Signal. Structural implication: automotive functional safety certification creates decade-scale commitments to certified IP; once automotive supply chains adopt ARM Cortex-R/A with ISO 26262 certification, replacement difficulty in that segment becomes very high. Analyst interpretation.

Source-Governed Fact Table

Factual Claims With Source Attribution

All factual claims used in this dossier are recorded in the following table. Claims not appearing here are explicitly analyst interpretation. Source tier definitions follow the Dispatch Intelligence Standard: T1 (primary/authoritative), T2 (recognized institutional), T3 (reputable secondary).

Claim Source / Reference Tier Date Checked Confidence Why It Matters
ARM Holdings founded November 1990 as Advanced RISC Machines Ltd., a joint venture of Acorn Computers, Apple Computer, and VLSI Technology ARM corporate history — ARM official investor relations (arm.com) T1 2026-06-09 High Establishes the founding premise of the architecture licensing model — the structural separation of architecture specification from chip manufacturing that defines ARM's shovel-layer position.
SoftBank Group acquired ARM Holdings in 2016 for approximately £23.4 billion Regulatory approval records — UK FCA and public company disclosures; reported in financial and technology press T1 2026-06-09 High Documents the ownership transition that preceded the NVIDIA acquisition attempt; relevant to the governance and neutrality analysis in Section 4 (Historical Position) and Section 8 (Replacement Difficulty).
NVIDIA announced acquisition of ARM Holdings from SoftBank in September 2020 for approximately $40 billion (per NVIDIA press release, September 2020); deal abandoned February 2022 following regulatory opposition from UK CMA, European Commission, and US FTC UK Competition and Markets Authority (CMA) investigation announcement; European Commission competition review; US Federal Trade Commission administrative proceedings; NVIDIA and SoftBank company statements T1 2026-06-09 High The regulatory blocking is itself a structural signal: competition regulators from three major jurisdictions assessed ARM's neutrality as a structural precondition for its licensing position. This is the clearest external validation that regulators treat ARM as infrastructure-layer rather than competitive product.
ARM Holdings re-listed on NASDAQ in September 2023, trading under the ticker ARM; SEC Form 20-F filed as primary disclosure document ARM Holdings Form 20-F (SEC filing, 2023) — NASDAQ and SEC records T1 2026-06-09 High Re-establishes ARM as a public company with SEC disclosure requirements; the 20-F filing is a primary source for ARM's business model, revenue structure, and customer concentration disclosures used throughout this dossier.
ARM's primary revenue model consists of upfront licensing fees and per-chip royalties; license types include Architecture Licenses (custom CPU design) and IP/Processor Licenses (pre-designed CPU cores) ARM Holdings Form 20-F (SEC filing, 2023) — business description and revenue recognition sections T1 2026-06-09 High Foundational structural fact: the per-chip royalty model is the mechanism by which ARM captures aggregate chip production volume regardless of which downstream applications or devices win. This is the primary basis for the Shovel classification.
Apple's transition from Intel x86 to Apple Silicon (ARM architecture) was announced at WWDC June 2020; the M1 launched November 2020; transition completed across Mac lineup by 2023 Apple official WWDC 2020 announcements and subsequent product announcements — Apple Newsroom (T1) T1 2026-06-09 High Documents the largest ISA migration in recent personal computing history; Apple's multi-year preparation confirms that platform-scale ISA migration requires significant lead time even for the world's most technically capable device company — primary support for the "High" replacement difficulty assessment.
Amazon Web Services (AWS) Graviton processors use ARM architecture; Graviton first announced 2018 with successive generations (Graviton2, Graviton3, Graviton4) AWS official press releases and AWS re:Invent announcements (T1) T1 2026-06-09 High AWS Graviton is the first major public cloud provider's confirmed ARM-architecture server processor program; documents the structural migration of cloud infrastructure workloads toward ARM architecture and extends ARM's shovel position into the cloud server market.
Google announced Axion processor (ARM-based, targeting Google Cloud infrastructure) in 2024; Microsoft announced Azure Cobalt 100 (ARM Neoverse-based) in 2023 Google Cloud official Next '24 announcement (T1); Microsoft Azure official announcement (T1) T1 2026-06-09 High Confirms that all three of the largest public cloud providers (AWS, Google, Microsoft) have publicly committed to ARM-architecture custom processors for cloud infrastructure — a structural migration signal that ARM's shovel position now extends to server and cloud compute, not only mobile and embedded.
NVIDIA Grace CPU (used in Grace Hopper superchip) uses ARM Neoverse V2 architecture NVIDIA official GTC and product announcements — NVIDIA Newsroom (T1) T1 2026-06-09 High NVIDIA — ARM's primary competitor during the failed 2020-2022 acquisition — became an ARM architecture licensee for its server CPU product, confirming that the commercial logic of ARM architecture adoption extends even to companies with the technical capability to build alternative ISA implementations. Relevant to the Shovel-layer breadth argument.
RISC-V is an open-source instruction set architecture governed by RISC-V International, a non-profit standards and governance body RISC-V International (riscv.org) — governance documentation and ISA specification T2 2026-06-09 High RISC-V is the primary structural alternative to ARM architecture and the reason ARM's Gatekeeper signal is classified as "moderate" rather than "strong." Its existence as an open, royalty-free standard maintained by a recognized standards body gives it structural credibility as an alternative path, especially for new platforms without legacy software compatibility requirements.
ARM announced Arm Total Design ecosystem in October 2022 to accelerate custom silicon development using ARM IP in partnership with EDA vendors, foundries, and cloud companies ARM official press release, October 2022 (T1) T1 2026-06-09 High Confirms ARM's deliberate expansion from IP licensor to ecosystem orchestrator for custom silicon; documents the strategic initiative to lower the barrier to ARM architecture adoption for new custom chip programs — relevant to the Compounding Dynamics section and to future classification of ARM's ecosystem depth.
ARM states in its investor and marketing materials that its technology is present in the substantial majority of smartphones globally; this is a self-reported figure and is not independently verified in this dossier ARM Holdings investor materials and official marketing (T1 for the claim's existence as ARM's public statement; Moderate Confidence for precision of specific percentage figures) T1 2026-06-09 Moderate ARM's self-reported smartphone penetration is the primary quantitative basis for the mobile market dominance claim. Confidence labeled Moderate rather than High because the specific percentage is self-reported marketing data; the structural claim that ARM architecture dominates mobile computing is directionally consistent with the independently-confirmed customer list (Apple, Qualcomm, MediaTek, Samsung) above.
ARM Holdings plc listed simultaneously on the London Stock Exchange and NASDAQ in April 1998 Company and exchange historical records — London Stock Exchange and NASDAQ filings; ARM corporate history (arm.com investor relations) T1 2026-06-09 High Establishes the 1998 public listing as the point at which ARM's architecture licensing model became a public market structure and the mobile semiconductor ecosystem began consolidating around ARM's ISA — relevant to the historical narrative in Section 4.
Scanner Interpretation

Reading the Signal Scores

This section explains how the ten scanner signals translate into ARM's classification. The goal is to make the classification legible, auditable, and reproducible using the Shovel Scanner. The key structural contrast with other dossier cases is explained explicitly: ARM's Gatekeeper signal is lower than TSMC's or ASML's because of the RISC-V alternative, which no manufacturing or equipment layer has an equivalent for.

Signal Values Used in Classification
Enables Many (enablesMany)89 / 100
Chases Visible (chasesVisible)16 / 100
Controls Access (controlsAccess)72 / 100
Near Core Infra (nearCoreInfra)94 / 100
Failure Disrupts (failureDisrupts)82 / 100
Hard to Switch (hardToSwitch)82 / 100
Dependency Grows (dependencyGrows)86 / 100
Necessity Not Spec (necessityNotSpec)88 / 100
Replaceable (replaceable)34 / 100
Compounds Integrations (compoundsIntegrations)80 / 100

Signals Driving the Primary Classification

Four signals produce the dominant Shovel classification force: nearCoreInfra (94) — processor architecture is the foundational layer beneath every computing device, more upstream than any application, platform, or even most manufacturing infrastructure. necessityNotSpec (88) — chip designers cannot begin a processor design program without choosing an ISA; this is architectural necessity, not market speculation. enablesMany (89) — ARM licenses architecture and IP to Apple, Amazon, Google, Microsoft, Qualcomm, MediaTek, Samsung, NVIDIA, NXP, and hundreds of other chip designers simultaneously across unrelated markets. dependencyGrows (86) — IoT expansion, automotive electrification, cloud infrastructure migration, and AI edge inference all add ARM-architecture chip volume.

The Structural Contrast: Why ARM Differs From TSMC and ASML

The most important signal comparison in this dossier is replaceable: ARM scores 34, compared to TSMC's score of 8 and ASML's effectively equivalent position. TSMC and ASML have no credible alternatives at leading-edge — no other company makes EUV lithography machines (ASML), and no other foundry produces advanced node chips at comparable yield and volume (TSMC). ARM has RISC-V: an open-source, royalty-free ISA with genuine and growing adoption in embedded systems, AI accelerators, and early cloud implementations.

This difference directly drives the Gatekeeper score: ARM's controlsAccess (72) reflects real ISA compatibility lock-in, but not monopoly-class access control. Analysts calibrating ARM against TSMC or ASML should hold this distinction explicitly: ARM's structural position is strong and durable, but is contestable in a way that TSMC's manufacturing position is not. The Shovel primary classification, however, is not sensitive to this difference — the dominant Shovel signals (nearCoreInfra, enablesMany, necessityNotSpec, dependencyGrows) do not depend on the absence of RISC-V. Analyst interpretation.

How Signal Changes Would Affect Classification

If RISC-V achieves dominant adoption in a major device segment — for example, if a major smartphone SoC vendor ships at volume on a RISC-V-primary architecture — replaceable would rise toward 50–60 and controlsAccess would fall toward 55–60. This would reduce the Gatekeeper secondary score from 73 to approximately 60–65, weakening the Hybrid classification toward "Shovel with limited Gatekeeper characteristics." The Shovel primary classification (88) would not change materially: even in a world where RISC-V captures 30–40% of new chip design starts, ARM would still enable a large and growing base of chip volume. Analyst interpretation: the Shovel primary is more durable than the Gatekeeper secondary in ARM's structural position — an important distinction for long-horizon classification analysis.

Analyst Use Cases

Who Uses This Dossier and For What

01
Technology Sector Analyst — Mapping Semiconductor IP Infrastructure
An analyst building a map of the semiconductor supply chain uses this dossier to understand where ARM sits relative to TSMC (manufacturing), ASML (equipment), and chip designers (fabless). The dossier places the architecture licensing layer structurally: upstream of chip design, downstream of ISA specification standards, orthogonal to manufacturing. This placement is necessary to avoid misclassifying ARM as a chip company, a software company, or an equipment company — it is none of these.
02
Platform Builder — Evaluating ISA Commitment Before Chip Design
An engineer or product leader evaluating whether to build a custom chip on ARM architecture, RISC-V, or x86 uses this dossier to understand the full switching cost structure before committing to an ISA. The analysis of software ecosystem lock-in (Section 5), the Architecture License vs. IP License distinction (Section 6), and the replacement difficulty assessment (Section 8) provide structured inputs for an architectural decision that will constrain the product for years.
03
Supply Chain Researcher — Understanding the Architecture Layer in Computing
A researcher building a dependency map of modern computing infrastructure uses this dossier to establish where the architecture licensing layer sits and what it connects to. The dependency map (Section 7) provides structured upstream and downstream nodes. The dossier explicitly connects ARM to TSMC (manufacturing), ASML (equipment through TSMC), NVIDIA, Apple, and cloud hyperscalers — establishing ARM's position as one of several critical IP layers that must function for modern computing to operate.
04
Policy Analyst — Understanding Open vs. Licensed Architecture Standards
A policy researcher examining semiconductor supply chain governance uses this dossier to understand the structural difference between ARM (a licensed, proprietary ISA with commercial royalties) and RISC-V (an open-source, royalty-free ISA governed by a non-profit international body). The dossier's treatment of the NVIDIA acquisition collapse — and its regulatory interpretation — provides structural context for why semiconductor architecture licensing is treated as infrastructure policy, not merely commercial IP.
05
Framework Student — Understanding Shovel-Gatekeeper Classification at the IP Layer
A reader learning the Shovel Economy Framework uses ARM as a reference case for how IP licensing creates a shovel-layer position: ARM earns from aggregate chip volume without competing in any chip market. The Gatekeeper secondary signal — ISA compatibility lock-in moderated by RISC-V — demonstrates why "moderate" and "strong" gatekeeper classifications are structurally distinct, and why the presence of a credible alternative changes the classification meaningfully.
Limits and Uncertainty

What This Dossier Does Not Claim

Explicit statement of dossier limits. A dossier with clearly stated uncertainty is more valuable than one with false confidence. Analysts should weigh these limits before applying this dossier to any consequential decision.

This Dispatch dossier is a structural classification record. It is not investment advice, a financial recommendation, or a valuation. No claim in this document should be used as the sole basis for any financial decision. The classification of ARM as a Hybrid Shovel/Gatekeeper asset describes structural market-layer position, not financial performance, future revenue, or shareholder returns.
Related Dispatch Cases

Structural Cross-References

Related Blog Primers

Foundational Reading

PDF Dossier

Dossier Format Status

PDF version pending. This dossier currently meets the content requirements of the Dispatch Intelligence Standard but has not yet been formatted for the PDF dossier standard described in Section 6 of DISPATCH_INTELLIGENCE_STANDARD.md. PDF production requires a minimum of 10 source-governed fact table entries (current fact table: 13 entries) and a completed language and classification accuracy review. PDF will be issued in a subsequent governance cycle once a print-safe layout is prepared. No PDF is available at the time of publication. Do not link to a PDF version of this dossier from external sources — no such file exists.
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System Navigation

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Dispatch 010 is a node in the full ShovelsSale analytical system. The Shovel Economy Framework provides the structural model used to classify ARM's layer position. The Shovel Scanner allows analysts to reproduce or challenge the classification by adjusting individual signal values. The Dispatch archive contains the full layered atlas of which this dossier is one node.